1. Field of the Invention
The invention relates to a clock data recovery (CDR) circuit and, in particular, to a mixed mode controlled oscillator base CDR circuit.
2. Description of the Related Art
A clock data recovery circuit plays an important role in high speed Serializer/Deserializer (SERDES) design. With greater demand for lower chip costs and more highly integrated designs, requirements for reduced chip area and power has resulted in adoption of more advanced process technologies. Nevertheless, for a conventional analog CDR circuit, area and power do not scale well with process because core devices therein can not be used as loop filters due to gate oxide current leakage, as the leakage makes the control voltage of the loop filters unstable during the absence of incoming data. In addition, generally, designing analog circuits with low voltage consumes more area and current.
Recently, all digital CDR solutions have been published, which attempt to resolve the above-mentioned problems. Drawbacks of the all digital CDR solutions are (1) difficulties in scaling with process due to requirement for the multiple phase generator, which is an analog circuit, typically a PLL or DLL, (2) phase quantization error, (3) greater area and power consumption due to the requirement for the phase interpolator to generate smaller phase resolution, and (4) loop latency.